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Loading... Toggle navigation Run Stop Save Copy Submit Support email is support@edaplayground.com . Playgrounds Log In x Warning! This exercise has been opened in another tab; autosave has been disabled. Close this tab or refresh to reactivate. Brought to you by Languages & Libraries Testbench + Design SystemVerilog/Verilog VHDL Specman e + SV/Verilog Python + SV/Verilog Python only C++/SystemC Perl Csh UVM / OVM None UVM 1.2 UVM IEEE 1800.2-2017 UVM 1.1d OVM 2.1.2 Other Libraries None OVL SVUnit SVAUnit 3.0 ClueLib 0.6.1 svlib 0.5 Enable TL-Verilog Enable Easier UVM Enable VUnit Libraries None OVL OSVVM UVVM Top entity Enable VUnit Specman Specman 2023.09 Libraries None SystemC 2.3.3 Tools & Simulators Select... Aldec Riviera Pro 2023.04 Cadence Xcelium 23.09 Siemens Questa 2023.3 Synopsys VCS 2023.03 Aldec SyntHESer 2023.05 Siemens Precision 2023.1 GHDL 3.0.0 Icarus Verilog 12.0 Yosys 0.37 C++ Perl Python Csh VTR 7.0 GPL Cver 2.12.a VeriWell 2.8.7 Compile Options Run Options Compile Options Run Options Use run.bash shell script Compile Options Run Options Run Time: Use run.do Tcl file Compile Options Run Options Run Time: Compile Options Run Options Run Time: Use run.do Tcl file Use run.bash shell script Compile Options Run Options Run Time: Use run.do Tcl file Use run.bash shell script Global Options Compile Options Run Options Run Time: Use run.do Tcl file Use run.bash shell script Global Options Compile Options Run Options Run Time: Use run.do Tcl file Use run.bash shell script Import Options Make Options Run Options Simulator Options Use run.bash shell script Compile Options Run Options Use run.do Tcl file Use run.bash shell script Compile Options Run Options Use run.do Tcl file Use run.bash shell script Compile Options Run Options Use run.do Tcl file Use run.bash shell script Compile Options Run Options Use run.do Tcl file Use run.bash shell script use ABC with cell library memory -nomap fsm -nomap skip FSM step Use run.ys file instead Show diagram after run Show netlist after run Show diagram after run Show HTML after run Compile Options Select... C++98 C++03 C++11 C++14 C++17 Use -pedantic -Wall -Wextra Run Options Use run.bash shell script Use run.bash shell script Arguments Arguments Open EPWave after run Show output file after run Output File Name Download files after run Examples using EDA Playground VHDL Verilog/SystemVerilog UVM EasierUVM SVAUnit SVUnit VUnit (Verilog/SV) VUnit (VHDL) TL-Verilog e + Verilog Python + Verilog Python Only C++/SystemC Community Collaborate Forum Follow @edaplayground 205 testbench.sv Hide Preview design.sv Hide Preview Log Share Submit Public (anyone with the link can view) Published (will appear in search results) Private (only you can view) Save Filename must match regex: ^[a-zA-Z0-9_-]+[a-zA-Z0-9_.-]*$ File already exists Filename cannot start with "testbench." or "design." URL can not be empty. Please enter valid URL. Please enter file name. Please enter valid file type. File Image Video Filename Create file or Upload files... (drag and drop anywhere) File Name (Allowed extensions: jpg, jpeg, png, svg) Image URL Insert Image URL File Name (Allowed extensions: mp4) Video URL Insert Video URL Filename Filename must match regex: ^[a-zA-Z0-9_-]+[a-zA-Z0-9_.-]*$ File already exists Filename cannot start with "testbench." or "design." Please enter valid file extension. Filename must match regex: ^[a-zA-Z0-9_-]+[a-zA-Z0-9_.-]*$ File already exists Filename cannot start with "testbench." or "design." URL can not be empty. Please enter valid URL. Please enter file name. Please enter valid file type. File Image Video Filename Create file or Upload files... (drag and drop anywhere) File Name (Allowed extensions: jpg, jpeg, png, svg) Image URL Insert Image URL File Name (Allowed extensions: mp4) Video URL Insert Video URL Filename Filename must match regex: ^[a-zA-Z0-9_-]+[a-zA-Z0-9_.-]*$ File already exists Filename cannot start with "testbench." or "design." Please enter valid file extension. Please confirm to remove: Please confirm to remove: × Available Apps EDA Playground EPWave Close × Error Close × Info Close × EPWave Examples Trivial Example RAM from EDA Playground OpenCores Example Close × Validation Error Close × User Validation Required Your account is not validated. If you wish to use commercial simulators, you need a validated account. If you have already registered (or have recently changed your email address), but have not clicked on the link in the email we sent you, please do so. If you cannot find the email, please check your spam/junk folder. Or click here to resend the email. If you have not already registered for a full account, you can do so by clicking below. You will then need to provide us with some identification information. You may wish to save your code first . Validate your account × Not Supported During Collaboration Creating, deleting, and renaming files is not supported during Collaboration. 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